Suchergebnisse

Over the last decade, hardware Trojans have gained increasing attention in academia, industry and by government agencies. In order to design reliable countermeasures, it is crucial to understand how hardware Trojans can be built in practice. This is an area that has received relatively scant treatment in the literature. In this thesis, we examine how particularly stealthy parametric Trojans can be introduced to VLSI circuits. Parametric Trojans do not require any additional logic and are purely based on subtle manipulations on the sub-transistor level to modify the parameters of few transistors which makes them very hard to detect. We introduce a design methodology to insert stealthy parametric hardware Trojans which are based on injecting extremely rare path delay faults into the netlist of the target circuit. As a case study, we apply our method to a 32-bit multiplier circuit resulting in a stealthy Trojan multiplier that computes faulty outputs for specific combinations of input pairs that are applied to the circuit. The multiplier can be used to realize bug attacks, introduced by Biham et al. in 2008. We also extend this concept and show how it can be used to attack ECDH key agreement protocols. Our method is a versatile tool for designing stealthy Trojans for a given circuit and is not restricted to multipliers and the bug attack. In this thesis we also examine how a stealthy side-channel hardware Trojan can be inserted in a provably-secure side-channel analysis protected implementation. Once the Trojan is triggered, the malicious design exhibits exploitable side-channel leakage leading to successful key recovery attacks. The underlying concept is based on a secure masked hardware implementation which does not exhibit any detectable leakage. However, by running the device at a particular clock frequency one of the requirements of the underlying masking scheme is not fulfilled anymore, and the device's side-channel leakage can be exploited. We apply our technique to a Threshold Implementation of the PRESENT block cipher realized in both FPGA and ASIC. We show that triggering the Trojan makes both FPGA and ASIC prototypes vulnerable to certain SCA attacks. True random number generators (TRNGs) are an essential component of cryptographic designs, which are used to generate private keys for encryption and authentication, and are used in masking countermeasures. This thesis also presents a mechanism to design a stealthy parametric hardware Trojan for ring oscillator-based TRNGs. When the Trojan is triggered by operation at a specific high temperature the malicious TRNG generates predictable non-random outputs, yet under normal operating conditions it works correctly. Also we elaborate a stochastic model based on Markov Chains by which the attacker can use their knowledge of the Trojan to predict the TRNG outputs.

Diese Studie hat die Technologiepolitik als Ergebnis von Zusammenarbeit zwischen Staat und Industrie seit dem II. Weltkrieg in Japan zum Gegenstand. Nachdem aus historischer Perspektive in diese Thematik eingeführt wurde, wird anhand des "Very Large Scale Integrated Circuits Project (VLSI)" die Thematik im einzelnen behandelt. Im letzten Kapitel wird die "Engineering Research Association" als politisches Instrument für Basisforschung in der Technologie vorgestellt. (DÜI-Xyl)

Minimizing the power consumption of electronic systems is one of the most critical concerns in the design of integrated circuits for very large-scale integration (VLSI). Despite the reality that VLSI design is known for its compact size, low power, low price, excellent dependability, and high functionality, the design stage remains difficult to improve in terms of time and power. Several optimization algorithms have been designed to tackle the present issues in VLSI design. This study discusses a bi-objective optimization technique for circuit partitioning based on a genetic algorithm. The motivation for the proposed research is derived from the basic concept that, if some portions of a circuit's system are deactivated during the processor's idle time, the circuit's power consumption is automatically reduced. To reduce the overall system's power consumption, maximization of sleep time and minimization of net cuts are required. To achieve these, an effective fitness function has been constructed in such a way that the balance criteria are also maintained. The approach has been tested on a set of net lists from the ISPD'98 benchmark suite, each containing 10 to 30 nodes. The experimental results are compared with two existing methods that clearly indicate the acceptability of the suggested method. The suggested strategy achieves an average reduction of 24.69% and 31.46% for net cut, whereas average extensions of 15.20% and 12.31% are observed in sleep time when compared with two existing methods. The proposed method also achieves an average power efficiency of 14.98% and 12.09% with respect to these two state-of-the-art methods.

Unmanned Aerial Vehicle (UAV) swarm applications, algorithms, and control strategies have experienced steady growth and development over the past 15 years. Yet, to this day, most swarm development efforts have gone untested and thus unimplemented. Cost of aircraft systems, government imposed airspace restrictions, and the lack of adequate modeling and simulation tools are some of the major inhibitors to successful swarm implementation. This thesis examines how the OpenEaagles simulation framework can be extended to bridge this gap. This research aims to utilize Hardware-in-the-Loop (HIL) simulation to provide developers a functional capability to develop and test the behaviors of scalable and modular swarms of autonomous UAVs in simulation with high confidence that these behaviors will prop- agate to real/live ight tests. Demonstrations show the framework enhances and simplifies swarm development through encapsulation, possesses high modularity, pro- vides realistic aircraft modeling, and is capable of simultaneously accommodating four hardware-piloted swarming UAVs during HIL simulation or 64 swarming UAVs during pure simulation.

The development of globalized semiconductor manufacturing processes and supply chains has lead to an increased interest in hardware security as new types of hardware based attacks, called hardware Trojans, are being observed in industrial and military electronics. To combat this, a technique was developed to help analyze hardware designs at the register-transfer-level (RTL) and locate points of interest within a design that might be vulnerable to attack. This method aims to eventually enable the creation of an end-to-end design hardening solution that analyzes existing designs and suggests countermeasures for potential Trojan attacks. The method presented in this work uses a set of base heuristics to evaluate the signals and logic within an RTL design. These signals and their assignments are ranked according to different heuristic selection criteria to determine if they belong to one of three types for potential behavior modification Trojans. The first type aims to identify locations for highly destructive Trojans that could completely inhibit device function. The second corresponds to locations where an intermittent issue could be created, such as errors in calculation edge cases. The final type considers critical signals used to connect submodules within a design, potentially limiting communication or injecting false data into calculations if attacked. Once ranked, the top-most location for each of these three groups is reported in a ranked list. From this list, markers can be automatically placed in copies of the original design files to indicate where a potential Trojan attack could occur. This approach was validated by using it to analyze two hardware designs. The results were investigated manually, where high-level understanding of the designs was used to evaluate the potential implications of each location selected. This validation demonstrated that this automatic process can not only identify signals and locations similar to what a domain-expert might select for Trojan insertion manually but can also ...

In this paper, we analyze, design, develop and evaluate 3-dimensional (3-D) wireless vehicular ad hoc network that is applicable to both civil applications and mission critical military applications. Furthermore, we present secure and privacy-aware communication techniques for 3-D vehicular wireless ad hoc networks. The main motivation of this work is that recent studies have shown that the road/traffic accidents and congestion are one of the major problems being faced in the US and all over the world. According to US Department of Transportation, road accidents and traffic jams result in over a billion dollars in lost work hours and fuel. According to National Highway Traffic and Safety Administration, (refer to http://www-fars.nhtsa.dot.gov) in 2012 there were 31,561 total fatalities due to road accidents. With the implementation of real-time information dissemination techniques using wireless networks, it is expected to help reduce road accidents and fuel consumption by providing timely information. With the implementation of autonomous communication systems between vehicles, either on the ground or in the air, it is possible to relay vital information that will save lives. Wireless communication is regarded as a backbone for the Intelligent Transportation System (ITS) to provide upcoming traffic information for safety and to support infotainment applications for passengers. Furthermore, we investigate the wireless communication requirement for real-time vehicular communications with security and low delay. With the successful implementation of reliable and trustworthy information dissemination mechanism, 3-D ad hoc network will help save fuel, money, time and lives. We also present an integration of vehicular ad hoc networks (VANETs – network of vehicles on the road) with UAV (flying vehicular) networks to form 3-D wireless network (as a proof of concept). We present numerical results obtained from simulations and experiments to support our claims. We present a point to multipoint, or mesh network, for 3-dimensional wireless vehicular ad hoc networks.

The major concern for the governments and private network communication is the security of systems against eavesdropping and illegal access. To overcome such illegal access the security of modern computer systems uses public-ciphers key namely Rivest, Shamir and Adleman (RSA). The RSA provides both authentication and secrecy of communication. In conventional encryption method the cryptography using RSA provides good secrecy and reduces area but generates more delay due to time taken by the multiplication part. To overcome such a problem, a 32-bit RSA using modulo (2n+1) multiplication based VLSI architecture is presented in this study. This method offers less delay with high performance which can be used in any communication network field. The proposed method is implemented using Xilinx 12.4 ISE and simulated in MODELSIM 6.3c.