Suchergebnisse

We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 32 pixels. The convolution processor operates on a pixel array of size 32 32, but can process an input space of up to 128 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second. ; This work was supported by Spanish Research under Grant TIC2003-08164-C03-01 (SAMANTA) and by the European Union under EU Grant IST-2001-34124 (CAVIAR). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science. ; Peer reviewed

Comunicación presentada al "19th IEEE International Conference on Electronics, Circuits and Systems" celebrada en Sevilla (España) del 9 al 12 de Diciembre del 2012. ; This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations. ; This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from European Community, TEC2011-24319 project from the Spanish Government, and P08-TIC-03674 project from the Andalusian Regional Government (with support from the PO FEDER). P. Brox is supported under the post-doctoral program called Juan de la Cierva from the Spanish Ministry of Science and Innovation. ; Peer Reviewed

Trabajo presentado al 23rd DCIS celebrado en grenoble del 12 al 14 de noviembre de 2008. ; This paper presents a fully differential 8th order transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V). ; This work has been founded in part by the EC through the project A109-Medea+ WITNESS (Wireless technologies for small area networks with embedded security and safety), the Spanish Regional Government of Junta de Andalucía under project TIC-927 and the Spanish Government under project TEC2007-68072. ; Peer reviewed

et al. ; This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. © 2009 IEEE. ; This work was supported by the European Commission under Grant IST-2001-34124 (CAVIAR). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science under FPU scholarship. The work of L. Camuñas-Mesa was supported by the Spanish Ministry of Education and Science under FPI scholarship. ; Peer Reviewed