Suchergebnisse

The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs. ; Ministerio de Economía y Competitividad TEC2017-87052-P ; Ministerio de Economía y Competitividad PID2020-116664RB-I00 ; Junta de Andalucía Projectos US-1380876 y US-1380823 ; European Union's Horizon 2020 Grant Agreement No. 95262 and No. 804476

We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 32 pixels. The convolution processor operates on a pixel array of size 32 32, but can process an input space of up to 128 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second. ; Gobierno de España TIC2003-08164-C03-01 ; European Union IST-2001-34124

This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, information is represented by a continuous flow of self-timed asynchronous events. Such events can be processed on the fly by event-based convolution chips, providing at their output a continuous event flow representing the 2-D filtered version of the input flow. In this paper we present a 32 × 32 pixel 2-D convolution event processor whose kernel can have arbitrary shape and size up to 32 × 32. Arrays of such chips can be assembled to process larger pixel arrays. Event latency between input and output event flows can be as low as 155 ns. Input event throughput can reach 20 Meps (mega events per second), and output peak event rate can reach 45 Meps. The chip can be configured to discriminate between two simulated propeller-like shapes rotating simultaneously in the field of view at a speed as high as 9400 rps (revolutions per second). Achieving this with a frame-constraint system would require a sensing and processing capability of about 100 K frames per second. The prototype chip has been built in 0.35 CMOS technology, occupies 4.3 × 5.4 and consumes a peak power of 200 mW at maximum kernel size at maximum input event rate. ; European Union 216777 ; Gobierno de España TEC2006-11730-C03-01, TEC2009-10639-C04-01 ; Junta de Andalucía P06TIC01417

Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multibit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation. ; Ministerio de Economía y Competitividad TEC2016-80549-R ; European Union FCT: UIDB/50021/2020 ; European Union LISBOA- 01-0145-FEDER-031901 (PTDC/CCI-COM/31901/2017, HiPErBio)

Tradicionalmente, la seguridad en los dispositivos criptográficos estaba ligada exclusivamente a la fortaleza del algoritmo. El nivel de seguridad venía determinado por la formulación matemática y la longitud de la clave. Sin embargo, la implementación física de los circuitos criptográficos tiene fugas de información como pueden ser el consumo de potencia o la radiación electromagnética, que puede ser explotadas por potenciales hackers para revelar la clave secreta. Uno de los ataques más potentes es el que se basa en análisis del consumo de potencia, conocido como Differential Power Analysis (DPA) attack. El DPA utiliza la dependencia del consumo de potencia con los datos procesados para revelar información. Para proteger los circuitos criptográficos se utilizan ampliamente estilos de lógica diferencial con un consumo de potencia (casi) constante. En este trabajo se proponen diferentes metodologías de diseño de celdas diferenciales mediante la redistribución de la carga almacenada en los nodos internos, eliminando el efecto memoria que aparece como un agujero importante en la seguridad. Las celdas propuestas eliminan la carga residual en el circuito y simplifican la estructura de la celda. Para demostrar la ganancia en prestaciones, se han diseñado, implementado físicamente y caracterizado experimentalmente estas celdas en la tecnología de TSMC de 90nm. Los resultados experimentales muestran una reducción del 15% en el área, del 11% en el consumo de potencia y sin degradación en el retraso de las puertas propuestas. Para demostrar la mejora en seguridad, se han desarrollado ataques DPA basados en simulación. ; Proyecto de I+D+i PID2020-116664RB-I00 ; MCIN/ AEI 10.13039/501100011033 ; Programa Operativo FEDER 2014-2020 / Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía proyecto US- 1380823 ; SPIRS (Secure Platform for ICT Systems Rooted at the Silicon Manfacturing Process) / European Union's Horizon 2020 Grant Agreement No. 952622

La inserción de fallos y en concreto los análisis diferenciales de fallos (Differential Fault Analysis – DFA) se han convertido en uno de los principales métodos para explotar las vulnerabilidades de los cifradores de bloque utilizados en multitud de aplicaciones. En este trabajo se presenta un nuevo esquema de protección basado en generar firmas de los registros internos utilizando códigos de Hamming. Esto permite cubrir un gran número de tipos de fallos, detectando tanto cambios a nivel de bit pares e impares, así como cambios a nivel de byte, los cuales son los fallos explotables por los DFAs. Como caso de estudio, el esquema presentado se ha aplicado al cifrador de bloque estándar Advanced Encryption Standard (AES) implementado utilizando T-boxes. Los resultados obtenidos sugieren un alto nivel de cobertura de fallos con un coste de consumo de recursos del 16% y sin ninguna penalización en la degradación de frecuencia. ; MCIN/AEI/ PID2020-116664RB-I00 ; FEDER 2014-2020 and Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía Project US- 1380823 ; European Union's Horizon 2020 / SPIRS (Secure Platform for ICT Systems Rooted at the Silicon Manfacturing Process) Project with Grant Agreement No. 952622

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. ; European Commission IST-2001-34124