Suchergebnisse

Comunicación presentada al "ISCAS 2012" celebrado en Seúl (Corea del Sur) del 20 al 23 de Mayo del 2012. ; Distance calculation is always one of the most important goals in a digital stereoscopic vision system. In an AER system this goal is very important too, but it cannot be calculated as accurately as we would like. This demonstration shows a first approximation in this field, using a disparity algorithm between both retinas. The system can make a distance approach about a moving object, more specifically, a qualitative estimation. Taking into account the stereo vision system features, the previous retina positioning and the very important Hold and Fire building block, we are able to make a correlation between the spike rate of the disparity and the distance. ; This work has been supported by the Spanish government granted project VULCANO (TEC2009-10639-C04-02) of the MICINN. ; Peer Reviewed

This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams ressemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50% AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64 times; 64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second. ; European Union IST-2001-34124 ; Gobierno de España TIC-2000-0406-P4, TIC-2003-08164-C03-01

This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating bidirectionally with all four neighbors. Address events include a module label. Each module includes an AER router which decides how to route address events. Two routing approaches have been proposed, analyzed and tested, using either destination or source module labels. Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance. Experimental results are given after testing the approach using high-end Virtex-6 FPGAs. The approach is proposed for both single and multiple FPGAs, in which case a special bidirectional parallel-serial AER link with flow control is exploited, using the FPGA Rocket-I/O interfaces. Extensive test results are provided exploiting convolution modules of 64 × 64 pixels with kernels with sizes up to 11 × 11, which process real sensory data from a Dynamic Vision Sensor (DVS) retina. One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with 262 × 103 neurons and almost 32 million synapses. ; Junta de Andalucía TIC- 6091 ; Ministerio de Economía y Competitividad TEC2009-106039-C04-01/02 ; European Union PRI-PIMCHI-2011-0768

Convolutional Neural Networks (ConvNets) are a particular type of neural network often used for many applications like image recognition, video analysis or natural language processing. They are inspired by the human brain, following a specific organization of the connectivity pattern between layers of neurons known as receptive field. These networks have been traditionally implemented in software, but they are becoming more computationally expensive as they scale up, having limitations for real-time processing of high-speed stimuli. On the other hand, hardware implementations show difficulties to be used for different applications, due to their reduced flexibility. In this paper, we propose a fully configurable event-driven convolutional node with rate saturation mechanism that can be used to implement arbitrary ConvNets on FPGAs. This node includes a convolutional processing unit and a routing element which allows to build large 2D arrays where any multilayer structure can be implemented. The rate saturation mechanism emulates the refractory behavior in biological neurons, guaranteeing a minimum separation in time between consecutive events. A 4-layer ConvNet with 22 convolutional nodes trained for poker card symbol recognition has been implemented in a Spartan6 FPGA. This network has been tested with a stimulus where 40 poker cards were observed by a Dynamic Vision Sensor (DVS) in 1 s time. Different slow-down factors were applied to characterize the behavior of the system for high speed processing. For slow stimulus play-back, a 96% recognition rate is obtained with a power consumption of 0.85mW. At maximum play-back speed, a traffic control mechanism downsamples the input stimulus, obtaining a recognition rate above 63% when less than 20% of the input events are processed, demonstrating the robustness of the network ; European Union 644096, 687299 ; Gobierno de España TEC2016-77785- P, TEC2015-63884-C2-1-P ; Junta de Andalucía TIC-6091, TICP1200

Neuromorphic vision sensors detect changes in luminosity taking inspiration from mammalian retina and providing a stream of events with high temporal resolution, also known as Dynamic Vision Sensors (DVS). This continuous stream of events can be used to extract spatio-temporal patterns from a scene. A time-surface represents a spatio-temporal context for a given spatial radius around an incoming event from a sensor at a specific time history. Time-surfaces can be organized in a hierarchical way to extract features from input events using the Hierarchy Of Time-Surfaces algorithm, hereinafter HOTS. HOTS can be organized in consecutive layers to extract combination of features in a similar way as some deep-learning algorithms do. This work introduces a novel FPGA architecture for accelerating HOTS network. This architecture is mainly based on block-RAM memory and the non-restoring square root algorithm, requiring basic components and enabling it for low-power low-latency embedded applications. The presented architecture has been tested on a Zynq 7100 platform at 100 MHz. The results show that the latencies are in the range of 1 µs to 6.7 µs, requiring a maximum dynamic power consumption of 77 mW. This system was tested with a gesture recognition dataset, obtaining an accuracy loss for 16-bit precision of only 1.2% with respect to the original software HOTS. ; Spanish government and the European Regional Development Fund COFNET TEC2016-77785-P ; Spanish government and the European Regional Development Fund MIND-ROB PID2019-105556GB-C33

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available. ; European Union 320689, 604102, 644096, 687299 ; U.K. Engineering and Physical Sciences Research Council EP/G015740/1 ; Polish Ministry of Science and Higher Education 11.11.120.612 ; Ministerio de Economía y Competitividad TEC2012-37868-C04-01/02 , TEC2015- 63884-C2-1-P, TEC2016-77785-P ; Junta de Andalucía TIC-6091, P12-TIC-1300

et al. ; This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. © 2009 IEEE. ; This work was supported by the European Commission under Grant IST-2001-34124 (CAVIAR). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science under FPU scholarship. The work of L. Camuñas-Mesa was supported by the Spanish Ministry of Education and Science under FPI scholarship. ; Peer Reviewed

El glaucoma es una de las principales causas de ceguera. Cambia la morfología del nervio óptico. La copa es la región central del disco óptico. El CDR (relación del diámetro de la copa y el disco) es un indicador del estado de la enfermedad. Un CDR normal se encuentra entre 0.3 y 0.4. A mayor CDR Glaucoma más avanzado. En este trabajo se pretende demostrar la viabilidad de los algoritmos en los que la forma del disco y la copa son aproximadamente círculos. En estos casos el número de parámetros es mucho menor y, al menos, en nuestras pruebas iniciales la aproximación es más realista que con las formas originales para su implementación en aprendizaje profundo. ; Glaucoma is one of the main causes of blindness. It changes the morphology of the optic nerve. The cup is the central region of the optical disc. The CDR (ratio of the diameter of the cup and disc) is an indicator of the state of the disease. A normal CDR is between 0.3 and 0.4. A higher CDR more advanced glaucoma. In this work we try to demonstrate the viability of algorithms in which the shape of the disc and the cup are approximately circles. In these cases, the number of parameters is much lower and, at least, in our initial tests the approach is sometimes more realistic than with the original forms for a Deep learning implementation. ; NPP project funded by SAIT (2015-2018) ; Spanish government grant European Regional Development Fund COFNET TEC2016-77785-P

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. ; European Commission IST-2001-34124