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Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time. © 2013 Elsevier B.V. All rights reserved. ; This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from EuropeanCommunity, TEC2011-24319 project from the Spanish Govern-ment, and P08-TIC-03674 project from the Andalusian Regional Government (with support from the PO FEDER). P. Brox is supportedunder the post-doctoral program called 'Juan de la Cierva' from theSpanish Ministry of Science and Innovation. ; Peer Reviewed

This paper presents the application of soft computing techniques to video processing. Especially, the research work has been focused on the de-interlacing task. It is necessary whenever the transmission standard uses an interlaced format but the receiver requires a progressive scanning, as happens in consumer displays such as LCDs and plasma. A simple hierarchical solution that combines three simple fuzzy logic-based constituents (interpolators) is presented in this paper. Each interpolator is specialized in one of three key image features for de-interlacing: motion, edges, and possible repetition of picture areas. The resulting algorithm offers better results than others with less or similar computational cost. A very interesting result is that our algorithm is competitive with motion-compensated algorithms. ; This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from European Community, TEC2008- 04920 project from the Spanish Ministry of Science and Innovation, and by P08-TIC-03674 project from the Andalusian regional Government. ; Peer Reviewed

Trabajo presentado al Fuzzy Systems celebrado en Barcelona del 18 al 23 de julio de 2010. ; The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The xfsl tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation. ; This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from European Community, TEC2008-04920 from the Spanish Ministry of Science and Innovation, and P08-TIC-03674 from the Andalusian regional Government. ; Peer Reviewed

Comunicación presentada a la "12th International Conference Information Processing and Management of Uncertainty in Knowledge-Based Systems" celebrada en Malaga del 22 al 27 de Junio de 2008. ; This paper presents an algorithm for video de-interlacing. The approach uses three fuzzy logic-based systems to adapt the interpolation strategy to the presence of motion and edges. Furthermore, the algorithm is able to deal with any kind of TV material independently of the source used to acquire the scene. Extensive simulations of standard and real sequences prove the efficiency of the proposed algorithm. ; This work has been supported in part by the Spanish MEC Projects TEC2005-04359 and DPI2005-02293, and by the Projects TIC2006-635 and TEP2006-375 from the Andalusian regional Government. ; Peer Reviewed

Comunicación presentada al "WISP 2007" celebrado en Alcala de Henares del 3 al 5 de Octubre de 2007. ; A new motion adaptive algorithm for de-interlacing video is proposed in this paper. It employs two fuzzy systems to interpolate the missing lines of the transmission. One fuzzy system is used to evaluate the motion level at the current pixel, and a second one selects the most adequate temporal interpolation method. The combination of both systems provides an effective result with a low cost in term of hardware resources. ; This work has been supported in part by the Spanish CICYT Projects TEC2005-04359 and DPI2005-02293, and by the Projects TIC2006-635 and TEP2006-375 from the Andalusian regional Government. ; Peer Reviewed

Comunicación presentada a la "11th International Conference Information Processing and Management of Uncertainty in Knowledge-Based Systems" celebrada en Paris del 2 al 7 de Julio de 2006. ; Interlaced-to-progressive algorithms are currently required by video format conversion systems in order to display a progressive scanning used in modern visualization equipments. Deinterlacing algorithms use interpolation techniques to calculate missing pixels in transmitted fields. A motion adaptive algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion in the images is proposed in this paper. The performance of this new approach is evaluated by extensive simulation of different video sequences. ; This work has been partially funded by the projects TEC2005-04359/MIC from the Spanish Ministry of Education and Science and TIC2006-635 from the Andalusian Regional Government. The first author is also supported by the Spanish Ministry of Education under the program F.P.U. for Phd. Students. ; Peer Reviewed

Comunicación presentada a la "11th International Conference Information Processing and Management of Uncertainty in Knowledge-based Systems" celebrada en Paris del 2 al 7 de Julio de 2006. ; The increase of resolution is one of the most important tasks in image processing. Traditional interpolation algorithms perform a linear interpolation between the closest pixels in the image. This strategy may introduce mistakes specially in the reconstruction of edges and zones with high contrast luminance values. The use of a novel interpolation algorithm for image enlargement is presented in this paper. It employs a fuzzy logic-system to adapt the interpolation to the presence of edges in the image, achieving good results at expense of a low increment in the computational cost. ; This work has been partially funded by the project TEC2005-04359/MIC from the Spanish Ministry of Education and Science, and TIC2006-635 from the Andalusian Regional Government. The first author is supported by the Spanish ministry of Eductaion under the program F.P.U. for Phd. students. ; Peer Reviewed

[EN]: This paper describes a library (XSGImgLib) that includes parameterizable blocks to implement low-level image processing tasks on FPGAs. A modelbased design technique provided by Xilinx System Generator (XSG) has been used to design the blocks, which implement point operation (binarization) and neighborhood operations (linear and non-linear filtering) in grayscale images. The blocks are parameterizable for input/output data precision, window size, normalization strategy, and implementation options (area versus speed optimization). The paper includes the implementation results obtained after fixing these options and exemplifies the combination of several blocks of the library to build a complete design for image segmentation purposes. ; [ES]: Este artículo describe una biblioteca de bloques parametrizables (XSGImgLib) para la implementación de tareas de procesado de imágenes en FPGA. Se ha utilizado la técnica de diseño basado en modelos proporcionada por Xilinx System Generator (XSG) para diseñar diferentes bloques de procesado que implementan operaciones puntuales (binarización) y basadas en vecindad (filtros lineales y no-lineales) para imágenes en escala de grises. La parametrización de los bloques permite configurar la precisión de los datos de entrada/salida, el tamaño de la ventana, la estrategia de normalización y distintas opciones de implementación (optimización en área o velocidad). El artículo muestra los resultados de implementación para las diferentes opciones de configuración y ejemplifica la combinación de los bloques de procesado en el desarrollo de un sistema para segmentado de imágenes. ; The authors acknowledge the Spanish Agency for International Development (MAEC-AECID) for partially funding this work in the projects PCID/024124/09 and PCID/030769/10 (http://www.imse-cnm.csic.es/fortin). P. Brox is currently hired under the post-doctoral grant "Juan de la Cierva" from the Spanish government. ; Peer Reviewed

Trabajo presentado al "FUZZ-IEEE 2008" celebrado en Hong Kong del 1 al 6 de Junio de 2008. ; We address, by means of fuzzy linguistic summaries, two related problems: summarizing network flow statistics and making these statistics human-readable. Two complementary summarization methods are developed. First, a fixed set of protoforms of interest is defined, and the ones with a higher truth value are shown to the user as simple on-line summaries. This first method is suitable for real-time monitoring. Then, an association rules mining process is carried out in order to find hidden relations in flow records. Both approaches are implemented in a tool capable of real-time and off-line processing of network flow records. Experimental results for a number of heterogeneous NetFlow records show the usefulness of linguistic summaries to both network practitioners and users. ; This work has been supported in part by projects TEC2005-04359/MIC from the Spanish Ministry of Education and Science and project TIC2006-635 from the Andalusian regional Government. ; Peer Reviewed

Comunicación presentada al "DCIS 2007" celebrada en Sevilla del 21 al 23 de Noviembre de 2007. ; Soft computing techniques are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed communications equipment is however an open problem. This paper describes a platform for the development of fuzzy systems with applications to communications systems, namely network traffic analysis and control. An FPGA development board with PCI interface is employed to support an open platform that comprises open CAD tools as well as IP cores. For the development process, we set up a methodology and a CAD tools chain that cover from initial specification in a high-level language to implementation on FPGA devices. PCI compatible fuzzy inference modules are implemented as SoPC based on the open WISHBONE interconnection architecture. We outline results from the design and implementation of fuzzy analyzers and regulators for network traffic. These systems are shown to satisfy operational and architectural requirements of current and future high-performance routing equipment. ; This work has been supported in part by projects TEC2005-04359/MIC from the Spanish Ministry of Education and Science and TIC2006-635 from the Andalusian regional Government. ; Peer Reviewed

Comunicación presentada a la "11th International Conference Information Processing and Management of Uncertainty in Knowledge-based Systems" celebrada en Paris del 2 al 7 de Julio de 2006. ; A major research problem in Internet transport and network layers is the development of traffic regulation mechanisms that can cope with the requirements of a growing diversity of technologies, applications and services. This paper presents novel mechanisms for intelligent traffic scheduling in Internet routers by means of fuzzy logic based systems. A systematic design methodology, interpretability principles, evaluation over a broad range of network scenarios as well as practical implementation constraints have been considered. A comparative evaluation of results obtained by means of our fuzzy controllers as compared to that of traditional approaches is outlined. ; This work has been partially supported by projects TEC2005-04359/MIC from the Spanish Ministry of Education and Science as well as TIC2006-635 from the Andalusian Regional Government. ; Peer Reviewed

Comunicación presentada a la "IEEE International Conference on Fuzzy Systems" celebrada en Vancouver (Canadá) del 16 al 21 de Julio de 2006. ; End-to-end Internet packet dynamics is a complex problem for which models available to date are at best incomplete. A major research problem in Internet transport layer protocols is the development of rate control mechanisms that can cope with the requirements of a growing diversity of technologies, applications and services. This paper describes novel mechanisms for intelligent end-to-end traffic rate control in Internet by means of fuzzy systems. We first outline a fuzzy logic based generalization of TCP (Transport Control Protocol) rate control principles. The design of a fuzzy TCP-like window-based rate controller is then described. A systematic fuzzy systems design methodology is used in order to simulate and implement the system as an experimental tool. A comparative evaluation of simulation and implementation results from the fuzzy rate controller as compared to that of traditional controllers is outlined. Besides being a useful modelling approach, the fuzzy rule based rate controller is shown to outperform other approaches with regards to a number of criteria. ; This work has been supported in part by projects TEC2005-04359/MIC from the Spanish Ministry of Education and Science and TIC2006-635 from the Andalusian regional Government. ; Peer Reviewed

Trabajo presentado al FUZZ celebrado en Barcelona del 18 al 23 de julio de 2010. ; This paper presents a design environment for the synthesis of embedded fuzzy controllers on FPGAs. It provides a novel implementation technique that allows accelerating the exploration of the design space of fuzzy control modules, as well as a codesign flow that eases their integration into complex control systems and the joint development of hardware and software components. The set of CAD tools supporting this environment includes specific fuzzy logic design tools provided by Xfuzzy, FPGA synthesis and implementation tools from Xilinx, and modeling and simulation facilities from Matlab. As demonstrated by the analyzed design examples, the described development strategy takes advantage of flexibility and ease of configuration offered by the different tools to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy control systems. ; This work was partially supported by projects FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from the European Community, TEC2008-04920 from the Spanish Ministry of Science and Innovation, and P08-TIC-03674 from the Andalusian regional Government. ; Peer Reviewed

Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to be a good alternative, both to face the security threats that arise as a consequence of the development of quantum computing and to allow efficient implementations of cryptographic primitives in resource-limited embedded systems, such as those used in consumer and industrial applications of the IoT. This article describes the hardware implementation of parameterized multi-unit serial polynomial multipliers to speed up time-consuming operations in NTRU-based cryptographic schemes. The flexibility in selecting the design parameters and the interconnection protocol with a general-purpose processor allow them to be applied both to the standardized variants of NTRU and to the new proposals that are being considered in the post-quantum contest currently held by the National Institute of Standards and Technology, as well as to obtain an adequate cost/performance/security-level trade-off for a target application. The designs are provided as AXI4 bus-compliant intellectual property modules that can be easily incorporated into embedded systems developed with the Vivado design tools. The work provides an extensive set of implementation and characterization results in devices of the Xilinx Zynq-7000 and Zynq UltraScale+ families for the different sets of parameters defined in the NTRUEncrypt standard. It also includes details of their plug and play inclusion as hardware accelerators in the C implementation of this public-key encryption scheme codified in the LibNTRU library, showing that acceleration factors of up to 3.1 are achieved when compared to pure software implementations running on the processing systems included in the programmable devices. ; European Union 952622 ; Ministerio de Ciencia e Innovación PID2020-116664RB100, 10.13039/501100011033

Interlacing techniques were introduced in the early analog TV transmission systems as an efficient mechanism capable of halving the video bandwidth. Currently, interlacing is also used by some modern digital TV transmission systems, however, there is a problem at the receiver side since the majority of modern display devices require a progressive scanning. De-interlacing algorithms convert an interlaced video signal into a progressive one by performing interpolation. To achieve good de-interlacing results, dynamical and local image features should be considered. The gradual adaptation of the de-interlacing technique as a function of the level of motion detected in each pixel is a powerful method that can be carried out by means of fuzzy inference. The starting point of our study is an algorithm that uses a fuzzy inference system to evaluate motion locally (FMA algorithm). Our approach is based on convolution techniques to process a fuzzy rulebase for motion-adaptive de-interlacing. Different strategies based on bi-dimensional convolution techniques are proposed. In particular, the algorithm called 'single convolution algorithm' introduces significant advantages: a more accurate measurement of the level of motion using a matrix of weights, and a unique fuzzification process after the global estimation, which reduces the computational cost. Different architectures for the hardware implementation of this algorithm are described in VHDL language. The physical realization is carried out on a RC100 Celoxica FPGA development board. © 2010 Elsevier B.V. ; This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from European Community, TIN2005-08943-C02-01 and TEC2008-04920 projects from the Spanish Government (with support from the European Regional Development Fund), and P08-TIC-03674 project from the Andalusian Regional Government. ; Peer Reviewed