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This work was supported by the European Union's ERA-NET CHIST-ERA 2018 research and innovation programme under grant agreement ANR-19-CHR3-0008. ; International audience ; Event cameras (or silicon retinas) represent a new kind of sensor that measure pixel-wise changes in brightness and output asynchronous events accordingly. This novel technology allows for a sparse and energy-efficient recording and storage of visual information. While this type of data is sparse by definition, the event flow can be very high, up to 25M events per second, which requires significant processing resources to handle and therefore impedes embedded applications. Neuromorphic computer vision and event sensor based applications are receiving an increasing interest from the computer vision community (classification, detection, tracking, segmentation, etc.), especially for robotics or autonomous driving scenarios. Downscaling event data is an important feature in a system, especially if embedded, so as to be able to adjust the complexity of data to the available resources such as processing capability and power consumption. To the best of our knowledge, this works is the first attempt to formalize event data downscaling. In order to study the impact of spatial resolution downscaling, we compare several features of the resulting data, such as the total number of events, event density, information entropy, computation time and optical consistency as assessment criteria. Our code is available online at https://github.com/amygruel/EvVisu.

This work was supported by the European Union's ERA-NET CHIST-ERA 2018 research and innovation programme under grant agreement ANR-19-CHR3-0008. ; International audience ; Event cameras (or silicon retinas) represent a new kind of sensor that measure pixel-wise changes in brightness and output asynchronous events accordingly. This novel technology allows for a sparse and energy-efficient recording and storage of visual information. While this type of data is sparse by definition, the event flow can be very high, up to 25M events per second, which requires significant processing resources to handle and therefore impedes embedded applications. Neuromorphic computer vision and event sensor based applications are receiving an increasing interest from the computer vision community (classification, detection, tracking, segmentation, etc.), especially for robotics or autonomous driving scenarios. Downscaling event data is an important feature in a system, especially if embedded, so as to be able to adjust the complexity of data to the available resources such as processing capability and power consumption. To the best of our knowledge, this works is the first attempt to formalize event data downscaling. In order to study the impact of spatial resolution downscaling, we compare several features of the resulting data, such as the total number of events, event density, information entropy, computation time and optical consistency as assessment criteria. Our code is available online at https://github.com/amygruel/EvVisu.

Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used for vision, AER sensors and processors are not restricted to capturing and processing still image frames, as in commercial frame-based video technology, but sense and process visual information in a pixel-level event-based frameless manner. As a result, vision processing is practically simultaneous to vision sensing, since there is no need to wait for sensing full frames. Also, only meaningful information is sensed, communicated, and processed. Of special interest for brain-like vision processing are some already reported AER convolutional chips, which have revealed a very high computational throughput as well as the possibility of assembling large convolutional neural networks in a modular fashion. It is expected that in a near future we may witness the appearance of large scale convolutional neural networks with hundreds or thousands of individual modules. In the meantime, some research is needed to investigate how to assemble and configure such large scale convolutional networks for specific applications. In this paper, we analyze AER spiking convolutional neural networks for texture recognition hardware applications. Based on the performance figures of already available individual AER convolution chips, we emulate large scale networks using a custom made event-based behavioral simulator. We have developed a new event-based processing architecture that emulates with AER hardware Manjunath's frame-based feature recognition software algorithm, and have analyzed its performance using our behavioral simulator. Recognition rate performance is not degraded. However, regarding speed, we show that recognition can be achieved before an equivalent frame is fully sensed and transmitted. ; This work was supported in part by the Spanish Ministry of Education and Science under Grant TEC-2006-11730-C03-01 (SAMANTA2), be the Andalusian regional government under Grant P06-TIC-01417 (Brain System), and by the European Union (EU) Grants IST-2001-34124 (CAVIAR) and 216777 (NABAB). The work of J. A. Pérez-Carrasco was supported by a doctoral scholarship as part of research project Brain System. ; Peer reviewed

We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 32 pixels. The convolution processor operates on a pixel array of size 32 32, but can process an input space of up to 128 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second. ; This work was supported by Spanish Research under Grant TIC2003-08164-C03-01 (SAMANTA) and by the European Union under EU Grant IST-2001-34124 (CAVIAR). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science. ; Peer reviewed

et al. ; This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. © 2009 IEEE. ; This work was supported by the European Commission under Grant IST-2001-34124 (CAVIAR). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science under FPU scholarship. The work of L. Camuñas-Mesa was supported by the Spanish Ministry of Education and Science under FPI scholarship. ; Peer Reviewed

International audience ; This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 871501. ARTIFICIAL INTELLIGENCE AT THE EDGE. NEUROMORPHIC COMPUTING ONN Architecture for 5 neurons neurons (oscillators) Synapse Array with 2D MoS 2 memristors MIT VO 2 oscillators 2D MoS 2 memristor Materials Modeling (DFT) Density of States (DOS) Mobility Effective Mass Semiclassical Transport Modeling (TCAD) Compact Modeling (SPICE) Devices Characteristics Compact Models

International audience ; This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 871501. ARTIFICIAL INTELLIGENCE AT THE EDGE. NEUROMORPHIC COMPUTING ONN Architecture for 5 neurons neurons (oscillators) Synapse Array with 2D MoS 2 memristors MIT VO 2 oscillators 2D MoS 2 memristor Materials Modeling (DFT) Density of States (DOS) Mobility Effective Mass Semiclassical Transport Modeling (TCAD) Compact Modeling (SPICE) Devices Characteristics Compact Models

International audience ; This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 871501. ARTIFICIAL INTELLIGENCE AT THE EDGE. NEUROMORPHIC COMPUTING ONN Architecture for 5 neurons neurons (oscillators) Synapse Array with 2D MoS 2 memristors MIT VO 2 oscillators 2D MoS 2 memristor Materials Modeling (DFT) Density of States (DOS) Mobility Effective Mass Semiclassical Transport Modeling (TCAD) Compact Modeling (SPICE) Devices Characteristics Compact Models

International audience ; This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 871501. ARTIFICIAL INTELLIGENCE AT THE EDGE. NEUROMORPHIC COMPUTING ONN Architecture for 5 neurons neurons (oscillators) Synapse Array with 2D MoS 2 memristors MIT VO 2 oscillators 2D MoS 2 memristor Materials Modeling (DFT) Density of States (DOS) Mobility Effective Mass Semiclassical Transport Modeling (TCAD) Compact Modeling (SPICE) Devices Characteristics Compact Models