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The article considers the fundamental works that exist in the Western anthropologicaland sociological literature, concerning the most referred to and discussedpolitical uses of the past in the theory of collective memory. According to someauthors, the past is mutable; it is made and remade for present use and based uponthe requirements of the present. Another school of thought believes that collectivememory experiences the changes that have occurred in the society, and what iseven more, the past itself alters our notions and comprehension, and not vice versa.The third, relatively small group of memory experts argues that the same presentcan bear different memories and different realia may carry the same memory.Thus collective memory is a dynamic and continuous process of discussions, whichflow through the time within the political culture. Neither of these theoreticalapproaches is of narrow or dogmatic character; they differ primarily in emphasis.

Operating systems have historically had to manage only a single type of memory device. The imminent availability of heterogeneous memory devices based on emerging memory technologies confronts the classic single memory model and opens a new spectrum of possibilities for memory management. Transparent data movement between different memory devices based on access patterns of applications is a desired feature to make optimal use of such devices and to hide the complexity of memory management to the end user. However, capturing memory access patterns of an application at runtime comes at a cost, which is particularly challenging for large-scale parallel applications that may be sensitive to system noise. In this work, we focus on the access pattern profiling phase prior to the actual memory relocation. We study the feasibility of using Intel's Processor Event-Based Sampling (PEBS) feature to record memory accesses by sampling at runtime and study the overhead at scale. We have implemented a custom PEBS driver in the IHK/-McKernel lightweight multi-kernel operating system, one of whose advantages is minimal system interference due to the lightweight kernel's simple design compared to other OS kernels such as Linux. We present the PEBS overhead of a set of scientific applications and show the access patterns identified in noise sensitive HPC applications. Our results show that clear access patterns can be captured with a 10% overhead in the worst-case and 1% in the best case when running on up to 128k CPU cores (2,048 Intel Xeon Phi Knights Landing nodes). We conclude that online memory access profiling using PEBS at large-scale is promising for memory management in heterogeneous memory environments. ; This work has been partially funded by MEXT's program for the Development and Improvement of Next Generation Ultra High- Speed Computer Systems under its subsidies for operating the Specific Advanced Large Research Facilities in Japan. This project has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska- Curie grant agreement No 708566 (DURO). ; Peer Reviewed ; Postprint (author's final draft)

Operating systems have historically had to manage only a single type of memory device. The imminent availability of heterogeneous memory devices based on emerging memory technologies confronts the classic single memory model and opens a new spectrum of possibilities for memory management. Transparent data movement between different memory devices based on access patterns of applications is a desired feature to make optimal use of such devices and to hide the complexity of memory management to the end user. However, capturing memory access patterns of an application at runtime comes at a cost, which is particularly challenging for large-scale parallel applications that may be sensitive to system noise. In this work, we focus on the access pattern profiling phase prior to the actual memory relocation. We study the feasibility of using Intel's Processor Event-Based Sampling (PEBS) feature to record memory accesses by sampling at runtime and study the overhead at scale. We have implemented a custom PEBS driver in the IHK/-McKernel lightweight multi-kernel operating system, one of whose advantages is minimal system interference due to the lightweight kernel's simple design compared to other OS kernels such as Linux. We present the PEBS overhead of a set of scientific applications and show the access patterns identified in noise sensitive HPC applications. Our results show that clear access patterns can be captured with a 10% overhead in the worst-case and 1% in the best case when running on up to 128k CPU cores (2,048 Intel Xeon Phi Knights Landing nodes). We conclude that online memory access profiling using PEBS at large-scale is promising for memory management in heterogeneous memory environments. ; This work has been partially funded by MEXT's program for the Development and Improvement of Next Generation Ultra High- Speed Computer Systems under its subsidies for operating the Specific Advanced Large Research Facilities in Japan. This project has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska- Curie grant agreement No 708566 (DURO). ; Peer Reviewed ; Postprint (author's final draft)

Rasmus Nilsson, University College London, reviews Constructions and Instrumentalization of the Past: A Comparative Study of Memory Management in the Region, edited by Ninna Mörner (CBEES, 2020).

The CBEES State of the Region Report 2020 reveals disturbing tendencies to control and politicize the past in several countries in Central and Eastern Europe. Also, the report documents the great extent to which authoritarian and authoritarian-leaning governments actively intervene in how crucial parts of their country's history are to be written, taught, researched, remembered, and commemorated – or neglected and ignored. Furthermore, the report discusses the failure of some governments to deal with restitution for past injustices, and the way some politicians forbid access to important state archives, hinder the teaching of the history of contemporary events, or withdraw funding to or even close down independent research institutions altogether.

In this article, we introduce a new concept in HERMES, the FP7 funded project in Europe, in developing technology innovations towards computer aided memory management via intelligent computation, and helping elderly people to overcome their decline in cognitive capabilities.In this project, an integrated computer aided memory management system is being developed from a strong interdisciplinary perspective, which brings together knowledge from gerontology to software and hardware integration. State‐of‐the‐art techniques and algorithms for image, video and speech processing, pattern recognition, semantic summarisation are illustrated, and the objectives and strategy for HERMES are described. Also, more details on the software that has been implemented are provided with future development direction.

In cloud environments, the VMs within the computing nodes generate varying memory demand profiles. When memory utilization reaches its limits due to this, costly (virtual) disk accesses and/or VM migrations can occur. Since some nodes might have idle memory, some costly operations could be avoided by making the idle memory available to the nodes that need it. In view of this, new architectures have been introduced that provide hardware support for a shared global address space that, together with fast interconnects, can share resources across nodes. Thus, memory becomes a global resource. This paper presents a memory capacity aggregation mechanism for cloud environments called vMCA (Virtualized Memory Capacity Aggregation) based on Xen's Transcendent Memory (Tmem). vMCA distributes the system's total memory within a single node and globally across multiple nodes using a user-space process with high-level memory management policies. We evaluate vMCA using CloudSuite 3.0 on Linux and Xen. Our results demonstrate a peak running time improvement of 76.8% when aggregating memory, and of 37.5% when aggregating memory and implementing our policies. ; This research has received funding from the European Union's Seventh Framework Programme for research, technological development and demonstration under grant agreement number 610456 (Euroserver). The research was also supported by the Ministry of Economy and Competitiveness of Spain (TIN2012-34557 and TIN2015-65316), HiPEAC Network of Excellence (ICT-287759 and ICT-687698), the FI-DGR Grant Program (2016FI-B-00947) of the Government of Catalonia and the Severo Ochoa Program (SEV-2011-00067) of the Spanish Government. ; Peer Reviewed ; Postprint (author's final draft)

In cloud environments, the VMs within the computing nodes generate varying memory demand profiles. When memory utilization reaches its limits due to this, costly (virtual) disk accesses and/or VM migrations can occur. Since some nodes might have idle memory, some costly operations could be avoided by making the idle memory available to the nodes that need it. In view of this, new architectures have been introduced that provide hardware support for a shared global address space that, together with fast interconnects, can share resources across nodes. Thus, memory becomes a global resource. This paper presents a memory capacity aggregation mechanism for cloud environments called vMCA (Virtualized Memory Capacity Aggregation) based on Xen's Transcendent Memory (Tmem). vMCA distributes the system's total memory within a single node and globally across multiple nodes using a user-space process with high-level memory management policies. We evaluate vMCA using CloudSuite 3.0 on Linux and Xen. Our results demonstrate a peak running time improvement of 76.8% when aggregating memory, and of 37.5% when aggregating memory and implementing our policies. ; This research has received funding from the European Union's Seventh Framework Programme for research, technological development and demonstration under grant agreement number 610456 (Euroserver). The research was also supported by the Ministry of Economy and Competitiveness of Spain (TIN2012-34557 and TIN2015-65316), HiPEAC Network of Excellence (ICT-287759 and ICT-687698), the FI-DGR Grant Program (2016FI-B-00947) of the Government of Catalonia and the Severo Ochoa Program (SEV-2011-00067) of the Spanish Government. ; Peer Reviewed ; Postprint (author's final draft)